Method and apparatus for addressing memory arrays

ABSTRACT

The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable

BACKGROUND OF THE INVENTION

The present disclosure relates generally to the fabrication of microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:

FIG. 1 is a schematic depiction illustrating a memory array being addressed with a chip enable signal per each memory module, as known in the art.

FIG. 2 is a schematic depiction illustrating a memory array being addressed with a single chip enable signal for an entire memory array, according to one embodiment of the present description.

FIG. 3 is a flow diagram of addressing a memory array with a single chip enable signal, according to one embodiment of the present description.

FIG. 4 is a flow diagram of initializing a memory system including addressing each memory array with a single chip enable signal, according to one embodiment of the present description.

FIG. 5 is a schematic depiction of a system in accordance with one embodiment of the present description.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

Embodiments of the present description relate to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable signal.

FIG. 1 shows a non-volatile memory array 102, as known in the art, comprising, for illustration purposes, four (4) memory modules 104 ₀, 104 ₁, 104 ₂, and 104 ₃, each having four (4) memory units or microelectronic memory chips (i.e. memory module 104 ₀ having memory units 106 ₀-106 ₃, memory module 104 ₁ having memory units 106 ₄-106 ₇, memory module 104 ₂ having memory units 106 ₈-106 ₁₁, and memory module 104 ₃ having memory units 106 ₁₂-106 ₁₅). It is understood that the four memory module by four memory unit per memory module (i.e. sixteen (16) total memory units) arrangement for the non-volatile memory array 102 of FIG. 1 is merely exemplary and may be any appropriate size (i.e. any appropriate number of memory modules and any appropriate number of memory units within each memory module). The memory modules (e.g. 104 ₀, 104 ₁, 104 ₂, 104 ₃, and the like) may hereinafter be collectively referred to as 104 _(n) (where n is any of a selected number of memory modules) and the memory units (e.g. 106 ₀-106 ₁₅, and the like) may hereinafter be collectively referred to as memory units 106 _(m) (where m is any of a selected number of memory units).

In order for a host controller (not shown) to properly access the memory modules 104 _(n) and its corresponding memory units 106 _(m) within each corresponding memory module 104 _(n) the host controller must address or identify each memory module 104 _(n) and memory units 106 _(m), within each memory module 104 _(n). This may be achieved by sending a chip enable signal (e.g. 110 ₀, 110 ₁, 110 ₂, and 110 ₃ (hereinafter collectively 110 _(n))) to each memory module 104 ₀, 104 ₁, 104 ₂, and 104 ₃, respectively. With the chip enable signal 110 _(n) and information regarding the memory units 106 _(m) that is hard coded within each memory module 104 _(n), each memory unit 106 _(m) can be uniquely addressed. The specific process for addressing each memory unit 106 _(n) by the host controller is well known in the art and will not be discussed herein.

Referring again to FIG. 1, the memory array 102 would require four (4) chip enable signals 110 _(n) to address each of the four (4) memory modules 104 _(n). Furthermore, if the size of the memory array 102 were enlarged to thirty-two (32) total memory units 106 _(m) with four (4) memory units 106 _(m) per memory module 104 _(n), eight (8) chip enable signals 110 _(n) would be required. If the size of the memory array 102 were enlarged to sixty-four (64) total memory units 106 _(n) with four (4) memory units 106 _(n) per memory module 104 _(n), sixteen (16) chip enable signals 110 _(n) would be required, and so on. With microelectronic devices incorporating an ever increasing amount of memory, the increasing number chip enable signals 110 _(n) required for addressing memory arrays 102 may become an issue. These issues can include, but are not limited to, increased host controller complexity, increased host controller size, increased space for board level routing, increased cost, capacity limitations, and the like, as will be understood to those skilled in the art.

FIG. 2 illustrates an embodiment of the present description wherein only a single chip enable signal is required to address an entire memory array, regardless of the number of memory modules or memory units. FIG. 2 shows a non-volatile memory array 202 comprising (for illustration purposes) four (4) memory modules 204 ₀, 204 ₁, 204 ₂, and 204 ₃, each having four (4) memory units or microelectronic memory chips per memory module (i.e. memory module 204 ₀ having memory units 206 ₀-206 ₃, memory module 204 ₁ having memory units 206 ₄-206 ₇, memory module 204 ₂ having memory units 206 ₈-206 ₁₁, and memory module 204 ₃ having memory units 206 ₁₂-206 ₁₅). It is understood that the four memory module by four memory unit per memory module (i.e. sixteen (16) total memory units) arrangement for the non-volatile memory array 202 of FIG. 2 is merely exemplary and may be any appropriate size (i.e. any appropriate number of memory modules and any appropriate number of memory units within each memory module). The memory modules (e.g. 204 ₀, 204 ₁, 204 ₂, 204 ₃, and the like) may hereinafter be collectively referred to as 204 _(n) (where n is any of a selected number of memory modules) and the memory units (e.g. 206 ₀-206 ₁₅, and the like) may hereinafter be collectively referred to as memory units 206, (where m is any of a selected number of memory units).

As shown in FIG. 2, a single chip enable signal 212 may be issued from a host controller 210 that may be connected in parallel with each of the memory modules 204 _(n) within a memory array 202. A first enable in/out signal 214 ₀ may be connected to a first memory module (illustrated as memory module 204 ₀ in FIG. 2) of the memory array 202 to facilitate addressing the memory module (e.g. memory module 204 ₀) and its respective memory units (e.g. memory units 206 ₀-206 ₃), as will be discussed. Each of the memory modules (e.g. memory modules 204 ₀-204 ₃) that are adjacent to one another may be sequentially connected with enable in/out signals (e.g. 214 ₁-214 ₃). Thus, as illustrated in FIG. 2, the first module 204 ₀ may be connect with a second enable in/out signal 214 ₁ to the second module 204 ₁, the second module 204 ₁ may be connected with a third enable in/out signal 2142 to the third module 204 ₂, and the third module 204 ₂ may be connected with a third enable in/out signal 214 ₂ to the fourth module 204 ₃. In the illustration of FIG. 2, the fourth module 204 ₃ may be the last memory module in the memory array 202 and may output a final enable in/out signal, shown as fourth enable in/out signal 214 ₄. The sequential connection of the memory modules 204 _(n) may effectively form a daisy chain, as will be understood to those skilled in the art.

FIG. 3 shows a flow diagram of a process 300 of sequentially addressing memory modules within a memory array using a single chip enable signal (as illustrated in FIG. 2). As shown in block 310, a memory array having a plurality of memory modules coupled in a daisy chain with enable in/out signals and a single chip enable signal coupled in parallel to each memory module may be provided. The daisy chain may comprise each memory module having an incoming enable in lout signal and which generates an outgoing enable in/out signal, and wherein adjacent memory modules may be sequentially coupled such that the outgoing enable in/out signal of a memory module may be the incoming enable in/out signal to an adjacent memory module.

As shown in block 320, the chip enable signal, the enable in/out signals between adjacent memory modules, and the final enable in/out signal from the memory array may be optionally driven to a first voltage. It is understood that the first voltage need not be driven.

As shown in block 330, an incoming enable in/out signal into the memory array may be driven to a second voltage, which differs from the first voltage, which selects a specific memory module. A memory module is “selected” when the incoming enable in/out signal is at a second voltage and its outgoing enable in/out signal is at a differing voltage, e.g. at the first voltage. It is understood the first voltage and the second voltage need only be detectably different from one another. Thus, the first voltage may be either higher or lower than the second voltage.

As shown in block 340, the selected memory module may be reset by a reset command sent by the host controller (e.g. reset command is only accepted by a selected memory module).

As shown in block 350, the selected memory module configuration information may be received by the host controller. This configuration identifies information for the memory units within the selected memory module, which may be hard-coded in the memory module.

As shown in block 360, the host controller may appoint a volume address to the selected memory module. The volume address for each memory module is shown in FIG. 2, as “Volume 0” for memory module 104 ₀, “Volume 1” for memory module 104 ₁ “Volume 2” for memory module 104 ₂, and “Volume 3” for memory module 104 ₃. The combination of a volume address for the memory module and the configuration information of the memory units, uniquely addresses each memory unit.

As shown in block 370, the outgoing enable in/out signal from the selected memory module may be set to the second voltage, which “deselects” that memory module. As shown in block 380, a determination is made as to whether another memory module exists in sequence. This may be achieved by a signal send by the host controller, such as a Read ID signal, to check for a response. It is understood that the setting the outgoing enable in/out signal from the selected memory need not mean that it is driven. Rather, it merely needs to not be at the first voltage and a subsequent memory module incoming enable in/out signal is allowed to pull up, as will be understood to those skilled in the art.

As shown in block 390, if another memory module exists the second voltage level of outgoing enable in/out signal from the previous memory module becomes the second voltage level of the incoming enable in/out signal for next memory module, which “selects” that memory module (i.e. the incoming enable in/out signal at a second voltage and the outgoing enable in/out signal at a first voltage), and block 330, block 340, block 350, block 360, and block 370 are repeated. If another memory module does not exist, then the addressing of the memory array ends. It is understood that the determination of whether another memory module exists in the daisy chain could be achieved by sending the last enable in/out signal back to the controller. However, this would require adding an additional signal or pin to the controller, as will be understood to those skilled in the art.

It will be understood that uniquely addressing the memory units in the manner described need only occur once during a single power cycle. Each power cycle will, of course, require addressing the memory units again in the manner described. It is also understood that the memory units could be re-addressed at any point during operation of a memory system, as desired. Furthermore, it is understood that although the volumes are illustrated as being appointed sequentially, they may be appointed in a predetermined non-sequential sequence, such as for layout reasons, or may be appointed randomly, such as for load level purposes, as will be understood to those skilled in the art.

FIG. 4 illustrates a process for utilizing a sequential addressing system 400 of the present description with a serial reset for memory modules within a memory array for addressing a memory system. As shown in block 410, a memory system may be provided which may comprise at least one memory array having a plurality of memory modules coupled in a daisy chain with enable in/out signals and a single chip enable signal coupled in parallel to each memory module. The daisy chain may comprise each memory module having an incoming enable in/out signal and which generates an outgoing enable in/out signal, wherein adjacent memory modules may be sequentially coupled such that the outgoing enable in/out signal of a memory module may be the incoming enable in/out signal to an adjacent memory module.

As shown in block 415, power may be applied to the memory system.

As shown in block 420, the chip enable signal (referred to in the art as “CE_n”) for one of the plurality of memory arrays, the enable in/out signals between adjacent memory modules associated with the memory array, and the final enable in/out signal from the memory array may be optionally driven to a first voltage. Again, it is understood that the first voltage need not be driven.

As shown in block 425, an incoming enable in/out signal into the memory array may driven to a second voltage, which differs from the first voltage, which selects a specific memory module. Again, a memory module is “selected” when the incoming enable in/out signal is at a second voltage and its outgoing enable in/out signal is at a differing voltage, e.g. at the first voltage. It is understood the first voltage and the second voltage need only be detectably different from one another. Thus, the first voltage may be either higher or lower than the second voltage.

As shown in block 430, the selected memory module may be reset by a reset command sent by a host controller. In one embodiment, a host controller may issue a read status command (referred to in the art as Read Status (70h) command) prior to any other command to indicate sequential reset for each memory module, the host controller may then issue a reset command (referred to in the art as Reset (FFh)) which resets the memory module connected to the chip enable (referred to in the art as CE_n (Host Target)) whose incoming enable in/out signal is at a second voltage and whose outgoing enable signal is at a first voltage.

As shown in block 435, the host controller may issue a read status command to the memory module. As will be understood by those skilled in the art, this may comprise issuing a Read Status (70h) command and waiting until the Status Register bit 6 or SR[6] is set to one.

As shown in block 440, the host controller may configure the memory module with identification of the memory units therein. In one embodiment, the host controller may issue commands, such as Read ID (identification of target specification support), Read Parameter Page (identification of memory modules organization, features, timings, and other behavioral parameters), and the like, as known in the art, to configure the memory module.

As shown in block 445, a volume address may be appointed to the selected memory module. In one embodiment, a “Set Feature” command with a “Feature Address of Volume Configuration”, as known in the art, may be issued by the host controller to appoint the volume address for the memory module whose incoming enable in/out signal is at a second voltage and whose outgoing enable signal is at a first voltage.

As shown in block 450, the outgoing enable in/out signal from the selected memory module may be set to the second voltage, which “deselects” that memory module. In one embodiment, this occurs after the Set Features command completes, and the memory module may be deselected (until a Volume Select command (referred to in the art as “E1h”) is issued that selects the Volume). It will be understood to those skilled in the art that the host will not issue another command to the memory module connected to the chip enable signal until after the busy time for Set Features and Get Features (i.e. “tFEAT”) has elapsed.

As shown in block 455, whether there is another memory module in the memory array may be determine. If another memory module is detected, the next memory module in the daisy chain is selected, as shown in block 460 and the operations of block 430, block 435, block 440, block 445, block 450, and block 455 are repeated for the detected memory module. As shown in block 465, if another memory module is not detected, then whether there is another unaddressed memory array in the memory system may be determined. If another unaddressed memory array is found or detected, then the next chip enable signal associate with a different memory array may be selected, as shown in block 470 and the operations of block 420, block 425, block 430, block 435, block 440, block 445, block 450, block 455, and block 465 are repeated until all memory arrays are addressed.

As shown in block 475, when no unaddressed memory arrays are found, the initialization process is completed. In one embodiment, initialization process is completed by a Volume Select command (E1h) issued following a chip enable signal (CE_n) transition from high to low to select the next Volume that is going to execute a command, as will be understood to those skilled in the art.

It is understood that the non-volatile memory units of the present description may include, but is not limited to NAND memory units (flash memory using NAND logic gates), NOR memory (flash memory using NOR logic gates) units, PCM (phase change memory) units, MRAM (magnetoresistive random access memory) units, and the like. In one specific embodiment of the present description, the non-volatile memory comprises NAND memory units.

FIG. 5 illustrates an example of a microelectronic system 500 utilizing the subject matter of the present description. The microelectronic system 500 may be any electronic device, including but not limited to portable devices, such as a portable computer, a mobile telephone, a digital camera, a digital music player, a web tablet, a personal digital assistant, a pager, an instant messaging device, or other devices, The microelectronic system 500 may be adapted to transmit and/or receive information wirelessly, such as through a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, and/or a cellular network.

The microelectronic system 500 may include a controller 510, an input/output (I/O) device 520 (e.g. a keypad, display, and the like), a memory 530, and a wireless interface 540 coupled to each other via a bus 550. It is understood that the scope of the present invention is not limited to embodiments having any or all of these components.

The controller 510 may comprise, for example, one or more microprocessors, digital signal processors, application specific integrated circuits, microcontrollers, or the like. The memory 530 may be used to store messages transmitted to or by system 500. The memory 530 may also optionally be used to store instructions that are executed by controller 510 during the operation of system 500, and may be used to store user data. The memory 530 may be a memory system, as discussed herein, comprising at least one memory array having a plurality of memory modules coupled in a daisy chain with enable in/out signals and a single chip enable signal coupled in parallel to each memory module. The daisy chain comprising each memory module having an incoming enable in/out signal and which generates an outgoing enable in/out signal, and wherein adjacent memory modules are sequentially coupled such that the outgoing enable in/out signal of a memory module is the incoming enable in/out signal to an adjacent memory module.

The I/O device 520 may be used by a user to generate a message. The system 500 may use the wireless interface 540 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of the wireless interface 540 may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.

By referencing the microelectronic system 500 of FIG. 5, one skilled in the art will understand that the microelectronic system 500 or a computer may include a computer program product stored on a computer readable memory or medium, wherein the computer program may be adapted to be executed on a computer to select a memory module within a memory array, appoint a volume to the memory module, and address memory units within each memory module using the volume identification and memory unit information hard coded in each memory module, in a manner discussed herein.

Furthermore, it will be understood to those skilled in the art that subject matter of the present description only requires two pins and is scalable for an infinite number of memory arrays, memory modules, and/or memory units. Furthermore, the initial enable in/out signal may be set to Vcc (supply voltage), which may allow for backward compatibility with existing host controllers, as will be understood to those skilled in the art.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof. 

1. A memory array, comprising: a plurality of memory modules coupled in a daisy chain with enable in/out signals; and a single chip enable signal coupled in parallel to each memory module.
 2. The memory array of claim 1, wherein the plurality of memory modules coupled in a daisy chain with enable in/out signals comprises a plurality of memory modules couple in a daisy chain wherein each memory module has an incoming enable in/out signal and generates an outgoing enable in/out signal, and wherein adjacent memory modules are sequentially coupled such that the outgoing enable in/out signal of a memory module is the incoming enable in/out signal to an adjacent memory module.
 3. The memory array of claim 1, wherein the plurality of memory modules each comprises at least one memory unit.
 4. The memory array of claim 3, wherein the at least one memory unit comprises at least one non-volatile memory unit.
 5. The memory array of claim 4, wherein the at least one non-volatile memory units comprises a NAND memory unit.
 6. A method of addressing a memory system, comprising: providing a memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module; optionally, driving the single chip enable signal, enable in/out signals between adjacent memory modules, and a final enable in/out signal from the memory array to a first voltage; driving an incoming enable in/out signal into the memory array to a second voltage to select a first memory module in the daisy chain; resetting the selected memory module; receiving configuration information for the selected memory module by the host controller; appointing a volume address to the selected memory module to address memory units within the memory module; setting an outgoing enable in/out signal for the selected memory module to the second voltage; determining whether another unaddressed memory module exists in the memory array; selecting the next memory module in the daisy chain when another unaddressed memory module exists; and repeating resetting the selected memory module, receiving configuration information for the selected memory module by the host controller, appointing a volume address to the selected memory module, setting an outgoing enable in/out signal for the selected memory module to the second voltage, and determining whether another memory module exists in the memory array, when another memory module exists.
 7. The method of claim 6, wherein appointing a volume address to the selected memory module comprises appointing a sequential volume address to the selected memory module.
 8. The method of claim 6, wherein appointing a volume address to the selected memory module comprises appointing a non-sequential volume address to the selected memory module.
 9. The method of claim 6, wherein appointing a volume address to the selected memory module comprises appointing a randomized volume address to the selected memory module.
 10. The method of claim 6, wherein providing a memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module comprises providing a memory system comprising at least one memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module.
 11. The method of claim 6, further including determining whether another memory array exists in the memory system after no further memory modules are detected; selecting an unaddressed memory array when another memory module is not detected; and repeating optionally driving the single chip enable signal, enable in/out signals between adjacent memory modules, and a final enable in/out signal from the memory array to the first voltage, driving an incoming enable in/out signal into the memory array to the second voltage to select a first memory module in the daisy chain, resetting the selected memory module, receiving configuration information for the selected memory module by the host controller, appointing a volume address to the selected memory module, setting an outgoing enable in/out signal for the selected memory module to the second voltage, and determining whether another memory module exists in the memory array, when another memory module exists, and determining whether another unaddressed memory array exists in the memory system when no further unaddressed memory modules are detected.
 12. The method of claim 11, further including completing an initialization process when no further unaddressed memory arrays are detected.
 13. A system, comprising: a controller; and at least one memory array comprising a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module.
 14. The system of claim 13, wherein the plurality of memory modules coupled in a daisy chain with enable in/out signals comprises a plurality of memory modules couple in a daisy chain wherein each memory module has an incoming enable in/out signal and generates an outgoing enable in/out signal, and wherein adjacent memory modules are sequentially coupled such that the outgoing enable in/out signal of a memory module is the incoming enable in/out signal to an adjacent memory module.
 15. The system of claim 13, wherein the plurality of memory modules each comprises at least one memory unit.
 16. The system of claim 15, wherein the at least one memory unit comprises at least one non-volatile memory unit.
 17. The system of claim 16, wherein the at least one non-volatile memory units comprises a NAND memory unit. 